1. Field of Invention
The present invention relates to a thin film transistor type display device. More specifically, the invention relates to a thin film transistor type display device in which thin film transistors are formed on a first substrate, wiring lines are formed on a second substrate, and an element chip including one or more thin film transistors is peeled off from the first substrate and transferred to the second substrate.
2. Description of Related Art
In a related art thin film transistor type display device provided with thin film transistors, wiring lines therebetween, and a supporting substrate, there are many cases where the thin film transistors form a part of the whole display device, and the wiring lines and the supporting substrate form the remaining part thereof. When a thin film transistor type display device is manufactured, through the same manufacturing processes, after the thin film transistors, the wiring lines, and the supporting substrate are integrated, highly complicated manufacturing processes are required to make highly functional thin film transistors. Thus, the manufacturing cost generally increases. However, highly complicated manufacturing processes are not required to make only the wiring lines and the supporting substrate, and the manufacturing cost thereof is low. If the thin film transistors, wiring lines, and supporting substrate can be separately made, and the desired quantity of thin film transistors can then be disposed, it is possible to reduce the average manufacturing cost of the thin film transistor type display device as a whole.
Therefore, other related art thin film transistor type display devices can be provided such that thin film transistors are formed on a first substrate, wiring lines are formed on a second substrate, and an element chip including one or more thin film transistors is peeled off from the first substrate and transferred to the second substrate. According to this method, since the desired quantity of thin film transistors can be disposed, it is possible to reduce the average manufacturing cost of the thin film transistor type display device as a whole. In addition, laser ablation or adhesive are used for the peeling or transferring process, respectively.
FIG. 1 is a schematic of a method of peeling and transferring an element chip. A peeling layer 12 is formed on a first substrate 11, thin film transistors 13 and connecting pads 14 are formed on the peeling layer 12, and an element chip 16, which is separated with separators 15, is formed. Wiring lines 18 and connecting pads 19 are formed on the second substrate 17, and they are coated with adhesive 1a. The first substrate 11 and the second substrate 17 are contact-bonded to each other, and the adhesive 1a is caused to flow, thereby electrically connecting the connecting pads 14 of the element chip 16 to the connecting pads 19 of the second substrate 17. The adhesive 1a does not flow to other adjacent element chips 16 due to the separators 15. The element chip 16, including one or more thin film transistors 13, is peeled off from the first substrate 11 by laser ablation with irradiation from a laser 1b, and is transferred to the second substrate 17.
FIG. 2 is a plan view of a related art element chip. An element chip 26 including one or more thin film transistors 25 includes a polycrystalline silicon layer 21, a first metal layer 22, a second metal layer 23, and contact holes 24. In the patterning processes of all the layers, normal stepper lithography is used, and a design rule with a line/space/alignment precision=5 μm/5 μm/5 μm is used. The thin film transistors 25 form a pixel circuit of organic light emitting diodes in the element chip 26. The reason why two metal layers, such as the first metal layer 22 and the second metal layer 23, are used is that the present thin film transistor type display device requires transverse and longitudinal bus lines in order to display two-dimensional images, and the bus lines should have low resistance to reduce the time constant and voltage drop therein in consideration of the actual size of the thin film transistor type display device. The area of the element chip 26 is 150 μm×85 μm=12750 μm2.
FIG. 3 is a schematic of a method of manufacturing a related art element chip. A peeling layer 32 is formed on a first substrate 31, and a base insulating film 33 is formed on the peeling layer 32. An amorphous silicon (a-Si) layer 34 is deposited using PECVD of SiH4, LPCVD of Si2H6, etc., and it is crystallized and patterned with laser irradiation 35 to obtain a polycrystalline silicon (poly-Si) layer 36. A gate insulating film 37 is deposited using PECVD or ECR-CVD of TEOS, etc., a resistive mask 39 is used to selectively implant dopant ions by ion implantation or ion doping 38, and source/drain regions 3a are formed. Gate metal is deposited and patterned to obtain gate electrodes 3b. The gate electrodes 3b are used to selectively implant dopant ions by ion implantation, ion doping 3c, etc., to form lightly doped drain regions (LDD) 3d. 
An interlayer insulating film 3e is deposited, and contact holes 3f are formed. Source/drain metal is deposited and patterned to obtain source/drain electrodes 3g. The source/drain electrodes 3g are also used as connecting pads. Thin film transistors 3h are obtained from the above processes. Finally, an element chip 3j is formed by the separation with separators 3i. Although only one element chip 3j is illustrated in FIG. 3, a number of element chips 3j is arranged.
On the other hand, the related art includes methods of manufacturing thin film transistors known as holographic lithography and dynamic auto focus (white light focus: WLF) systems. According to the holographic lithography method, in the patterning process of thin film transistors, a fine design rule, for example, 1.0 μm or less can be used. Further, according to the dynamic auto focus system, the surface swelling of a large substrate can be compensated for. As a result, the lithography can be made with high precision. (For example, as disclosed in T. Shimoda, et al, Tech. Dig. IEDM 1999, 289; S. Utsunomiya, et al, Dig. Tech. Pap. SID 2000, 916; T. Shimoda, Proc. Asia Display/IDW '01, 327; S. Utsunomiya, et al, Proc. Asia Display/IDW '01, 339; T. Shimoda, Dig. Tech. Pap. AM-LCD 02, 5; http://www.holtronic.ch).